The present invention relates to a microcomputer system which has a central processing unit, a read only memory, and a random access memory, and uses a plurality of timers which facilitate monitoring events within the microcomputer system at predetermined intervals.
A programmable timer which operates according to a stored program is used by a microcomputer system to monitor events within the microcomputer system at fixed intervals, the microcomputer system having a CPU (central processing unit), a ROM (read only memory) and a RAM (random access memory). Japanese Laid-Open Patent Application No. 55-76436 discloses a proposed microcomputer system having such a timer. This timer is called also a programmable software timer. In the proposed microcomputer system, the hardware size can be made smaller by using the programmable software timer.
In a conventional microcomputer system having a programmable timer function, an interrupt to the CPU take places at predetermined intervals. Once the CPU receives an interrupt signal, normal operations are temporarily suspended and a timer operation with respect to the programmable timer starts. This timer operation with respect to the programmable timer is performed within each of the intervals in accordance with a program stored in the ROM.
However, it is necessary that a microcomputer system such as a personal facsimile system having a relatively large number of data transfer paths for use with the memory uses a plurality of programmable timers to monitor events within the entire system. If a conventional programmable timer function is applied to such a microcomputer system, the CPU has to carry out the memory read, memory write and detection operations for all of the programmable timers within each of the predetermined intervals. Hence, the CPU processing load in such a case will be heavy, and the speed of the CPU processing of other tasks will become low when the programmable timers are active at the same time.
In addition, it is likely that an error of a timer start request takes place when the CPU has a time delay between the memory read operation and the memory write operation. FIG. 4 shows such an error of the timer start request when it is issued on a conventional microcomputer system. When the CPU receives a timer start request signal, a time setting value "50" is written to a prescribed memory location of the RAM. However, a memory read operation may be performed immediately before the timer start request, and it may be detected that the data read from the RAM is "0". In such a case, the CPU writes the value "0" to the memory location of the RAM as the result of the detection. That is, the time setting value "50" written to the RAM at the issue of the timer start request, is erroneously changed to "0" by the memory write operation. Accordingly, the conventional microcomputer system may suffer such a problem when the CPU has a time delay between the memory read and write and when the memory access operations interfere with the timer start request.